1 From 7ee4db50b10ab2d8fdfc4781f26b84041cf568d7 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Wed, 10 Mar 2010 10:38:20 -0800
4 Subject: [PATCH] i965: Fix the response len of masked sampler messages for 8-wide dispatch.
6 The bad response length would hang the GPU with a masked sample in a
7 shader using control flow. For 8-wide, the response length is always
8 4, and masked slots are just not written to. brw_wm_glsl.c already
9 allocates registers in the right locations.
11 Fixes piglit glsl-fs-bug25902 (fd.o bug #25902).
12 (cherry picked from commit f6d210c284751ac50a8d6358de7e75a1ff1e4ac7)
13 (cherry picked from commit dc8c0359448cdae7b367552ba58783c04b199778)
15 src/mesa/drivers/dri/i965/brw_eu_emit.c | 18 +++++++++++++++---
16 1 files changed, 15 insertions(+), 3 deletions(-)
18 diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
19 index f69d529..82f2fda 100644
20 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
21 +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
22 @@ -1290,7 +1290,7 @@ void brw_SAMPLE(struct brw_compile *p,
25 GLboolean need_stall = 0;
29 /*printf("%s: zero writemask??\n", __FUNCTION__); */
31 @@ -1327,8 +1327,14 @@ void brw_SAMPLE(struct brw_compile *p,
32 /* printf("need stall %x %x\n", newmask , writemask); */
35 + GLboolean dispatch_16 = GL_FALSE;
37 struct brw_reg m1 = brw_message_reg(msg_reg_nr);
40 + guess_execution_size(p->current, dest);
41 + if (p->current->header.execution_size == BRW_EXECUTE_16)
42 + dispatch_16 = GL_TRUE;
44 newmask = ~newmask & WRITEMASK_XYZW;
46 brw_push_insn_state(p);
47 @@ -1343,7 +1349,13 @@ void brw_SAMPLE(struct brw_compile *p,
49 src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
50 dest = offset(dest, dst_offset);
51 - response_length = len * 2;
53 + /* For 16-wide dispatch, masked channels are skipped in the
54 + * response. For 8-wide, masked channels still take up slots,
55 + * and are just not written to.
58 + response_length = len * 2;