mesa: Add 7.11-rc1 with intel unfuckage.

[gentoo-draconx.git] / media-libs / mesa / files / 0001-i965-gen4-Fix-GPU-hangs-since-the-program-streaming-.patch

diff --git a/media-libs/mesa/files/0001-i965-gen4-Fix-GPU-hangs-since-the-program-streaming-.patch b/media-libs/mesa/files/0001-i965-gen4-Fix-GPU-hangs-since-the-program-streaming-.patch
new file mode 100644 (file)
index 0000000..2b385d2
--- /dev/null
+++ b/media-libs/mesa/files/0001-i965-gen4-Fix-GPU-hangs-since-the-program-streaming-.patch
@@ -0,0 +1,40 @@
+From 804995807dfea9cbdbd676e52b95d42715101913 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Fri, 8 Jul 2011 15:30:48 -0700
+Subject: [PATCH] i965/gen4: Fix GPU hangs since the program streaming change.
+
+This was tricky.  We were doing a use-before-initialize of
+grf_reg_count, but the value usually got overwritten anyway -- when we
+didn't have to do a relocation (typical), or on gen5 when we didn't
+have relocations at all.
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38771
+Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
+(cherry picked from commit d03fdc4cdefdfdc5b59547945704c6037a5061c7)
+---
+ src/mesa/drivers/dri/i965/brw_vs_state.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
+index d5010a2..179ca19 100644
+--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
++++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
+@@ -47,6 +47,7 @@ brw_prepare_vs_unit(struct brw_context *brw)
+    memset(vs, 0, sizeof(*vs));
+ 
+    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
++   vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1;
+    vs->thread0.kernel_start_pointer =
+       brw_program_reloc(brw,
+                       brw->vs.state_offset +
+@@ -54,7 +55,6 @@ brw_prepare_vs_unit(struct brw_context *brw)
+                       brw->vs.prog_offset +
+                       (vs->thread0.grf_reg_count << 1)) >> 6;
+ 
+-   vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1;
+    vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
+    /* Choosing multiple program flow means that we may get 2-vertex threads,
+     * which will have the channel mask for dwords 4-7 enabled in the thread,
+-- 
+1.7.3.4
+