Add mesa-7.7.1_rc2 with i915kill patch.

[gentoo-draconx.git] / media-libs / mesa / files / 0001-i965-Fix-the-response-len-of-masked-sampler-messages.patch

diff --git a/media-libs/mesa/files/0001-i965-Fix-the-response-len-of-masked-sampler-messages.patch b/media-libs/mesa/files/0001-i965-Fix-the-response-len-of-masked-sampler-messages.patch
new file mode 100644 (file)
index 0000000..5aa9da2
--- /dev/null
+++ b/media-libs/mesa/files/0001-i965-Fix-the-response-len-of-masked-sampler-messages.patch
@@ -0,0 +1,64 @@
+From 7ee4db50b10ab2d8fdfc4781f26b84041cf568d7 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Wed, 10 Mar 2010 10:38:20 -0800
+Subject: [PATCH] i965: Fix the response len of masked sampler messages for 8-wide dispatch.
+
+The bad response length would hang the GPU with a masked sample in a
+shader using control flow.  For 8-wide, the response length is always
+4, and masked slots are just not written to.  brw_wm_glsl.c already
+allocates registers in the right locations.
+
+Fixes piglit glsl-fs-bug25902 (fd.o bug #25902).
+(cherry picked from commit f6d210c284751ac50a8d6358de7e75a1ff1e4ac7)
+(cherry picked from commit dc8c0359448cdae7b367552ba58783c04b199778)
+---
+ src/mesa/drivers/dri/i965/brw_eu_emit.c |   18 +++++++++++++++---
+ 1 files changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
+index f69d529..82f2fda 100644
+--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
++++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
+@@ -1290,7 +1290,7 @@ void brw_SAMPLE(struct brw_compile *p,
+               GLuint simd_mode)
+ {
+    GLboolean need_stall = 0;
+-   
++
+    if (writemask == 0) {
+       /*printf("%s: zero writemask??\n", __FUNCTION__); */
+       return;
+@@ -1327,8 +1327,14 @@ void brw_SAMPLE(struct brw_compile *p,
+          /* printf("need stall %x %x\n", newmask , writemask); */
+       }
+       else {
++       GLboolean dispatch_16 = GL_FALSE;
++
+        struct brw_reg m1 = brw_message_reg(msg_reg_nr);
+-       
++
++       guess_execution_size(p->current, dest);
++       if (p->current->header.execution_size == BRW_EXECUTE_16)
++          dispatch_16 = GL_TRUE;
++
+        newmask = ~newmask & WRITEMASK_XYZW;
+ 
+        brw_push_insn_state(p);
+@@ -1343,7 +1349,13 @@ void brw_SAMPLE(struct brw_compile *p,
+ 
+        src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW); 
+        dest = offset(dest, dst_offset);
+-       response_length = len * 2;
++
++       /* For 16-wide dispatch, masked channels are skipped in the
++        * response.  For 8-wide, masked channels still take up slots,
++        * and are just not written to.
++        */
++       if (dispatch_16)
++          response_length = len * 2;
+       }
+    }
+ 
+-- 
+1.6.4.4
+